A Low-Power and Area-Efficient Design of a Weighted Pseudorandom Test-Pattern Generator for a Test-Per-Scan Built-in Self-Test Architecture

A Low-Power and Area-Efficient Design of a Weighted Pseudorandom Test-Pattern Generator for a Test-Per-Scan Built-in Self-Test Architecture

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A test pattern generator generates a pseudorandom test pattern that can be weighted to reduce the fault coverage in a built-in self-test.The objective of this paper is to propose a new weighted TPG for a scan-based BIST architecture.The motivation of this work is to generate efficient weighted patterns for enabling scan chains with reduced power consumption and area.Additionally, the pseudo-primary seed of TPG is maximized to obtain a considerable length in the weighted pseudorandom patterns.

The maximum-length weighted patterns are executed by assigning separate weights to the specific scan chains using a weight-enabled clock.This approach 5 Piece Dining Room reduces the hardware overhead and achieves a low power consumption of 26.7 nW.Moreover, the proposed weighted TPG is applied in two different test-per-scan BIST architectures and achieves accurate results.

The weighted patterns are also generated with fewer switching transitions and higher fault coverages of 98.81% and 97.35% in two different BIST architectures.This process is observed with six other Shower Caps circuits under test as their scan chains.

The simulation results are tested with a SilTerra 0.13 μm process on the Mentor Graphics IC design platform.Furthermore, the proposed weighted TPG is enlarged to a higher bit TPG, which is compared to accomplish the performance strategies.The experimental results of the proposed TPG design are compared and tabulated with existing potential TPG designs.